SNUG Silicon Valley 2013 26 Synthesizing SystemVerilog
be done with case statements when using the full_case and parallel_case synthesis
directives. The
priority, unique0 and unique keywords also provide simulation checking, to
help ensure the optimized
if...else decisions will work as intended.
Recommendation — Use the appropriate SystemVerilog
priority, unique0 or unique
decision modifier instead of the synthesis full_case or parallel_case directives. Note,
however, that it is not always desirable to have the synthesis gate minimizations that can result
from either the synthesis directives or the corresponding decision modifiers. These decision
modifiers should be used with caution. Also note that these decision modifiers do not prevent
latches, and do not flag all conditions that might infer latches.
Note: The
unique0 case was not supported by VCS, DC or Synplify-Pro at the time this paper was
written.
5.5 Loop statements
The original Verilog language has three types of synthesizable loop constructs: for, repeat, and while.
Each of these loops requires adhering to specific coding restrictions in order to be synthesized. These
restrictions are outside the scope of this paper. SystemVerilog enhances the Verilog
for loop capabilities,
and adds two additional types of loops that are useful for modeling hardware designs at the RTL level.
The enhancements to
for loops are the ability to declare the loop control variable as part of the loop, and
the ability to have multiple initial assignments and multiple step assignments. Two example
SystemVerilog-style
for loops are:
for (int i=0; i<=15; i++) ... // i is declared as part of the loop
for (int i=0, j=15; j>0; i++, j--) ... // multiple loop control variables
The ability to declare the loop control variable(s) as part of the for loop is more than just a convenience. It
can prevent inadvertent, difficult-to-debug coding errors. With traditional Verilog, the loop control variable
must be declared outside of, and prior to, the loop. Typically, the variables are declared at the module level.
Complex modules often have more than one
always procedural block within the module that have for
loops. If each loop uses the same variable name for its control, i, for instance, the loops can collide, with
multiple loops modifying the same variable at the same time. The result can be bizarre simulation behavior
that is challenging to debug.
SystemVerilog adds a
do...while loop, with similar syntax and usage as its C language counterpart. The
do...while loop is synthesizable, with the same coding restrictions as Verilog while loops. The advantage
of
do...while over while is that the loop control is tested at the bottom of the loop, rather than at the top.
A bottom-testing loop guarantees that the loop will execute at least once, which helps ensure that any
variables assigned within the loop will be initialized.
SystemVerilog makes it easier to control the execution of loops. In complex logic, it is often necessary to
abort a pass through a loop when certain conditions exist, or to abort the loop completely. Traditional
Verilog could do this by using the
disable statement, but the syntax is awkward and non-intuitive.
SystemVerilog adds the C-like
break and continue statements, which make it simpler to control loop
execution. Using
break and continue, instead of disable, also makes code more self-documenting.
Note: SystemVerilog also adds a
foreach loop specifically for iterating through arrays and vectors. The
foreach loop was not supported by either DC or Synplify-Pro at the time this paper was written. See
section 12.2 for the advantages of
foreach loops.